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A 14.8μVRMS integrated noise output capacitor-less low dropout regulator with a switched-RC bandgap reference

机译:具有开关RC带隙基准的14.8μV RMS 集成噪声输出无电容低压降稳压器

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Achieving low noise is becoming an important requirement in linear supply regulators for RF and mixed-signal SoC applications. A low-noise, low dropout regulator using switched-RC bandgap reference and a multi-loop, unconditionally stable error amplifier for output capacitor-less operation is presented. Switched-RC sample-and-hold filtered bandgap reference and current-mode chopped error amplifier techniques are used for reducing output noise of the LDO. A switched capacitor notch filter is used to ensure chopping ripple free output voltage. The proposed techniques reduce the 10Hz to 100kHz integrated output noise of the LDO from 95.3uVrms to 14.8μVrms. The LDO delivers a maximum load current of 100mA with a dropout voltage of 230mV and quiescent current consumption of 40μA. It achieves a PSR of 50dB at 10kHz for programmable output voltage range of 1V-3.3V. Fabricated in a 0.25μm CMOS process, the LDO core occupies an area of 0.18mm.
机译:在RF和混合信号SoC应用的线性电源稳压器中,实现低噪声已成为一项重要要求。提出了一种低噪声,低压差稳压器,它使用开关式RC带隙基准和多环,无条件稳定的误差放大器来实现无电容器输出的工作。开关RC采样​​保持滤波带隙基准和电流模式斩波误差放大器技术用于降低LDO的输出噪声。开关电容器陷波滤波器用于确保斩波自由的输出电压。所提出的技术将LDO的10Hz至100kHz的集成输出噪声从95.3uVrms降低至14.8μVrms。 LDO的最大负载电流为100mA,压降为230mV,静态电流消耗为40μA。对于1V-3.3V的可编程输出电压范围,它在10kHz时可实现50dB的PSR。 LDO内核以0.25μmCMOS工艺制造,占地0.18mm。

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