TSV (Through Silicon Via) is the key component in fabricating 3D ICs and device packaging which has the advantages of lower power consumption, higher integration density and shorter interconnection length. TSV is a composite structure fabricated by process filling electroplated copper into etched silicon via, it consists of Cu/Ta/TaN/SiO/Si multiple interfaces with roughness formed in the via etching process. In the TSV structure, more difference in coefficient of thermal expansion between copper and silicon leads to high thermal stress and related reliability issues, but fewer TSV EM works have been reported. Thus, TSV test structure with M1 of aluminum and backside redistribution layer of copper was designed and tested to evaluate EM reliability performance. Generally, the void nucleation and growth induce resistance change, and then impact expected metal interconnection performance. In our study, an unfamiliar EM failure mechanism of TSV was observed. No typical void was found, but barrier damage and Cu diffusion were observed in test. From failure analysis result, it is considered that EM failure mechanism of TSV consists of several major stages, including (1) barrier damage, (2) Cu diffusion and (3) CuAl alloy form. With the CuAl alloy formed, resistance of metal interconnection increases, so it induces EM failure.
展开▼
机译:TSV(硅通孔)是制造3D IC和器件封装的关键组件,具有功耗低,集成度高和互连长度短的优点。 TSV是通过将电镀铜工艺填充到蚀刻过的硅通孔中而制成的复合结构,它由Cu / Ta / TaN / SiO / Si多个界面组成,在通孔蚀刻过程中形成了粗糙的表面。在TSV结构中,铜和硅之间的热膨胀系数差异越大,就会导致较高的热应力和相关的可靠性问题,但是已经报道了较少的TSV EM工作。因此,设计并测试了具有铝的M1和铜的背面重新分布层的TSV测试结构,以评估EM可靠性性能。通常,空隙成核和生长引起电阻变化,然后影响预期的金属互连性能。在我们的研究中,观察到了不熟悉的TSV EM失效机制。没有发现典型的空隙,但是在测试中观察到了屏障破坏和Cu扩散。从失效分析结果来看,TSV的EM失效机理包括以下几个主要阶段:(1)势垒破坏,(2)Cu扩散和(3)CuAl合金形态。随着形成的CuAl合金,金属互连的电阻增加,因此引起EM失效。
展开▼