Effects of various assembly and reliability stresses on chip to package interaction

摘要

Systematic analysis of assembly and reliability stresses on chip to package interaction is performed. The novel modeling methodology employs multilevel sequential simulations to trace stress evolution, elasto-plasticity model to capture plastic strain accumulation, and actual GDS layout to evaluate BEOL reliability. The crack driving force is found to continue increasing during package assembly and field application due to plastic strain accumulation. A more comprehensive board level testing and analysis is recommended for better accessing long term package structure reliability.