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Designing radiation hardened CMOS microelectronic components at commercial foundries: space and terrestrial radiation environments and device and circuit techniques to mitigate radiation effects

机译:在商业铸造的设计辐射硬化CMOS微电子元件:空间和地面辐射环境和装置和电路技术,以减轻辐射效应

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Summary form only given. When using microelectronic components in a radiation environment, such as those experienced by components in space, components used in nuclear reactors and components used for high-energy physics experiments, specific degradation mechanisms must be mitigated to assure proper component performance over the lifetime of the part. Over the last thirty years, the preferred method for fabricating radiation-hardened parts has been by using boutique, dedicated foundries with specialized processes. The approach is often referred to as hardening-by-process. However, due to the small demand for radiation-hardened components and the exponentially increasing costs of advancing along Moore's, the number of these dedicated foundries has decreased dramatically and they remain more than three generations behind state-of-the-art CMOS. Recently, a novel approach for fabricating radiation-hardened components at commercial CMOS foundries has been developed. In this approach, radiation hardness is designed into the component using non-standard transistor topologies, the addition of guard rings and the application of novel circuit techniques. This presentation began with a description of the space and terrestrial radiation environments, followed by a discussion on the effects of different radiation sources on CMOS technologies. This included a discussion on total-ionizing dose, single-event upsets, single-event latchup and single-event transient radiation effects. Specific non-standard transistor topologies and the application of guard bands to mitigate total dose effects were discussed. Circuit approaches to mitigating single-event effects were also presented. The application of these design approaches does not come without area and performance penalties, which were quantified as part of this presentation. Unique reliability issues associated with the application of hardness-by-design methodologies were also discussed. Finally, a discussion on mitigating terrestrial radiation effects was presented.
机译:仅给出摘要表格。当在辐射环境中使用微电子元件时,例如空间中的部件经历的那些,必须减轻用于高能物理实验的核反应堆和用于高能量物理实验的部件的组件,以确保在部分的寿命上确保适当的部件性能。在过去的三十年中,制造辐射硬化部件的首选方法是通过使用具有专门化工艺的精品。这种方法通常被称为逐个硬化。然而,由于对辐射的需求较小,并且沿着摩尔推进的指数增加成本,这些专用代工厂的数量急剧下降,而且在最先进的CMOS背后仍然超过三代。最近,已经开发出一种新的用于在商业CMOS铸造件上制造辐射硬化成分的新方法。在这种方法中,使用非标准晶体管拓扑设计,辐射硬度设计成部件,添加防护环和新型电路技术的应用。该演示始于空间和地面辐射环境的描述,然后讨论不同辐射源对CMOS技术的影响。这包括关于全电离剂量,单事件扰乱,单事件锁存器和单事件瞬态辐射效应的讨论。讨论了特定的非标准晶体管拓扑和保护条带来减轻总剂量效果的施加。还提出了减轻单事件效果的电路方法。这些设计方法的应用没有没有区域和绩效惩罚,这被定量为本演示文稿的一部分。还讨论了与应用硬度逐行方法相关的独特可靠性问题。最后,提出了关于减轻陆地辐射效应的讨论。

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