首页> 外国专利> CMOS DEVICES HARDENED AGAINST TOTAL DOSE RADIATION EFFECTS

CMOS DEVICES HARDENED AGAINST TOTAL DOSE RADIATION EFFECTS

机译:CMOS器件克服了总剂量辐射效应

摘要

A CMOS or NMOS device (10) has one or more n-channel FET's (12) disposed on a substrate (20), the device (10) being resistant to total dose radiation failures, the device (10) further including a negative voltage source (22), for applying a steady negative back bias to the substrate of the n channel FET's (12) to mitigate leakage currents in the device (10), thereby mitgating total dose radiation effects. A method for operating a CMOS or NMOS device (10) to resist total dose radiation failures, the device (10) having one or more n channel FET's disposed on a substrate (20), has the steps: (a) disposing CMOS or NMOS device (10) in a radiation environment, the radiation environment delivering a dose on the order of tens or hundreds of krad (Si) over the period of use of the CMOS device (10); and (b) applying a negative back bias to the substrate (20) of the NMOSFET's (10), at a voltage for mitgating leakage currents about the n channel FET's (12).
机译:CMOS或NMOS器件(10)具有布置在衬底(20)上的一个或多个n沟道FET(12),该器件(10)抵抗总剂量辐射故障,该器件(10)还包括负电压源(22),用于向n沟道FET(12)的衬底施加稳定的负反向偏压,以减轻器件(10)中的泄漏电流,从而减轻总剂量辐射效应。一种用于操作CMOS或NMOS器件(10)以抵抗总剂量辐射故障的方法,该器件(10)具有布置在衬底(20)上的一个或多个n沟道FET,其具有以下步骤:(a)布置CMOS或NMOS器件(10)在辐射环境中,该辐射环境在使用CMOS器件(10)的期间内传递数十或数百krad(Si)的剂量; (b)在用于减轻n沟道FET(12)周围的泄漏电流的电压下,向NMOSFET(10)的衬底(20)施加负的反向偏压。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号