FPGA design and implementation of Digital Up-Converter using quadrature oscillator

摘要

In this paper we design and implement a complex Digital Up-Converter (DUC) using a Xilinx Virtex6 FPGA. All the steps necessary to build such circuits are thoroughly described and some valuable hints on how to overcome problems during the design time are presented. We introduce a new approach for oscillator circuits, which are an important part of any DUC design. Such oscillator approach is stable, clean, accurate and easily tunable. It is also RAM memory efficient, consuming no block RAM and a small amount of logic.