Limitations of the stuck-at fault model as an accurate measure of CMOS IC quality and a proposed schematic level fault model

摘要

Limitations in current testability approaches have forced major compromises in IC fault modeling, test, and quality. The stuck-at fault model is inadequate to achieve very high quality. Meaningful CMOS fault models based on schematically extracted faults are presented. Unity observability, the ability to probe all nodes, is presented as a practical approach to effective use of these models.