This paper presents a 2.4-GHz all-digital phaselocked loop (ADPLL) frequency synthesizer for wireless applications. The ADPLL is built around a digitally controlled LC oscillator, and it covers the target frequency range with fine frequency resolution. In the feedback path, a high-speed topology is employed for the variable phase accumulator to count full cycles of the RF output. A simple technique based on a short delay line in the reference signal path effectively lowers power consumption of the time-to-digital converter (TDC) and reduces in-band spurs of the output spectrum. Fabricated in a 65-nm CMOS, the ADPLL has an active area of 0.24 mm2. Measured output frequency range is from 2.29 to 2.92 GHz. The worstcase phase noise at 1-MHz offset over the whole frequency range is −120 dBc/Hz when the PLL consumes 12 mW from a 1.2-V supply, and −112 dBc when power is lowered to 8 mW. The inband spurs are below −61 dBc, and far-off spurs below −57 dBc.
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