A 2.4-GHz Low-Power All-Digital Phase-Locked Loop

摘要

This paper presents an all-digital phase-locked loop (ADPLL) for the 2.4-GHz ISM band frequency synthesis. The ADPLL is built around a digitally controlled LC oscillator. In the feedback path, a high-speed topology is employed for the variable phase accumulator to count full cycles of the RF output. A simple technique based on a short delay line in the reference signal path allows the time-to-digital converter core to operate at a low duty cycle with about 95% reduction of its average power consumption. To allow direct frequency modulation, the ADPLL incorporates a two-point modulation scheme with an adaptive gain calibration. Fabricated in a 65-nm CMOS, the ADPLL has an active area of ${hbox {0.24~mm}}^{2}$. Measured phase noise at 1-MHz offset is $-hbox{120~dBc/Hz}$ with a power consumption of 12 mW, and $-{hbox {112~dBc}}$ with power consumption lowered to 8 mW. The integrated phase noise of the ADPLL is measured to be 1.7$^{circ} $ rms.