A 2.4 GHz Dual-Modulus Divide-by-127/128 Prescaler in 0.35 μm CMOS Technology

摘要

High speed design solution for high divide-by-value dual modulus prescaler remains a challenge in designing high frequency synthesizers in CMOS technology. This paper presents a dual-modulus divide-by-127/128 prescaler implemented in 0.35 μm CMOS technology operating at 2.4 GHz frequency. Unlike the conventional topologies, this design is based on a novel way of dual-modulus division using four transmission gates in critical path. It consumes 4.8 mW power from a 3 V supply. Measurement results are provided.