Architectural Issues in Base-Station Frequency Synthesizers

摘要

Base station frequency synthesizers have extremely stringent specifications in terms of low integrated RMS phase error and low lock time. Satisfying both these conflicting specifications demands the selection of the right architecture. At the same time, other significant issues such as spur suppression and tuning range necessitate the use of allied techniques. In this paper, the different architectural choices available for this application are compared vis-a-vis their respective benefits and drawbacks. A Dual-Loop-PLL-based architecture that meets very strict specifications is designed and simulated at 2GHz. This synthesizer has an integrated RMS phase error of 1° while having a phase noise of -120dBc/Hz @ 600kHz offset The lock time is 40μs, and the toning range is 100MHz.