Circuit, architecture and method for tracking loop bandwidth in a frequency synthesizer having a wide frequency range

摘要

Circuits, architectures, and methods for tracking a phase locked loop (PLL) configuration such that its VCO gain is essentially a linear function of its feedback divider factor over a wide frequency range. The circuit generally includes an oscillator loop having (2n+1) stages, where n is an integer of at least 1, and at least three of the stages comprise a delay circuit and a characteristic control circuit configured to (i) receive divider information and (ii) set or change a delay characteristic of the delay circuit in response to the divider information. The architectures generally relate to PLLs that include a circuit embodying one or more of the inventive concepts disclosed herein. The method generally includes the steps of generating a periodic signal from an oscillator, dividing the periodic signal by a first number, and setting a characteristic property of at least part of the oscillator in accordance with the first number. The present invention advantageously tracks changes to a PLL and adjusts the VCO gain dynamically and in a predictable and controllable manner in response to such changes. The present invention avoids noisy and/or complicated charge pump and/or filter designs, and advantageously improves PLL stability, reliability and/or performance.