Novel approaches to circuit timing

摘要

In conventional sequential digital design, flip-flops are used to separate combinational logic gates. Signal propagation across logic gates ends at flip-flops. Accordingly, the minimum clock period is determined by the maximum of combinational delays between flip-flops. This partitioning of combinational logic into stages reduces design complexity significantly. However, in modern high-performance designs where clock frequency is usually pushed to the limit, this strict logic separation by flip-flops sacrifices timing performance. In addition, the simple assumption that all combinational paths work within one clock period makes the task to prevent counterfeiting very challenging, because a netlist extracted from reverse engineering represents all the functional information and can be processed using a standard IC design flow and used to produce chips in different foundries illegally. In this paper, we demonstrate two techniques that loosen the conventional strict separation of logic gates with flip-flops to enhance circuit performance and to reinforce netlist security.