TIMING FAILURE REMEDYING APPARATUS FOR AN INTEGRATED CIRCUIT, TIMING FAILURE DIAGNOSING APPARATUS FOR AN INTEGRATED CIRCUIT, TIMING FAILURE DIAGNOSING METHOD FOR AN INTEGRATED CIRCUIT, INTEGRATED CIRCUIT, COMPUTER READABLE RECORDING MEDIUM RECORDED THEREON A TIMING FAILURE DIAGNOSING PROGRAM FOR AN INTEGRATED CIRCUIT, AND COMPUTER READABLE RECORDING MEDIUM RECORDED THEREON A TIMING FAILURE REMEDYING PROGRAM FOR AN INTEGRATED CIRCUIT

摘要

A timing failure remedying apparatus for an integrated circuit has a comparator which compares a value captured in a taking-out scan chain for reference through an operation of a processing core for reference according to a first clock signal with a value captured in a taking-out scan chain to be tested through an operation of a processing core to be tested according to a second clock signal, a diagnosing unit which determines a timing failure in the logic circuit to be tested on the basis of a result of comparison by the comparator, and an adjuster which adjusts at least either a second cycle or a delay amount of the second clock signal. It is possible to examine a position of the timing failure or the number of the timing failures in the integrated circuit diagnosed as that its logic is normal but the timing failure occurs therein.