An accelerator-aware microarchitecture simulator for design space exploration

摘要

Specialized hardware accelerator has emerged as an efficient approach to mitigate the issue of power wall. Most accelerator designs focus on accelerator RTL synthesis, and place little focus on the communications between core and accelerator, thereby potentially limiting overall system performance. This paper presents an accelerator-aware micro-architectural simulator that supports accelerator design using high-level language (HLL) description, e.g., C++. The paper also discusses the design of a complete software stack for the simulator, from programming model, user configurability, to power profiler. Designers can then use the tool to conduct case studies and make performance analyses for design space exploration.