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Microarchitecture modeling for design-space exploration.

机译:用于设计空间探索的微体系结构建模。

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To identify the best processor designs, designers explore a vast design space. To assess the quality of candidate designs, designers construct and use simulators. Unfortunately, simulator construction is a bottleneck in this design-space exploration because existing simulator construction methodologies lead to long simulator development times. This bottleneck limits exploration to a small set of designs, potentially diminishing quality of the final design.; This dissertation describes a method to rapidly construct high-quality simulators. In particular, it examines structural modeling as a means to reduce construction time because it eliminates redundant effort required to manage design complexity in many modeling approaches, including that of programming a simulator in a sequential language. The dissertation also describes how to overcome common limitations in structural modeling that increase construction time by precluding amortization of component specification effort across models via component-based reuse. First, some time-consuming to specify design portions do not benefit from reuse, the logic for managing stall signals (i.e., timing-control) chief among them. Second, components flexible enough to enjoy reuse are often not reused in practice because of the number of details that must be understood in order to instantiate them. This dissertation addresses these issues by: (1) Presenting new insight into timing-control that allows it to be partitioned amongst reusable components. (2) Describing the application of programming language techniques (such as polymorphism and aspect-oriented programming) to allow creation of easy to reuse flexible components. (3) Allowing models to be statically analyzable in the presence of the above features.; The techniques presented in this dissertation are embodied in the Liberty Simulation Environment (LSE). LSE users have seen over an order of magnitude reduction in model development time. Their models were of high-quality; they were accurate, had adequate simulation speeds, and were compatible with static techniques for visualization and optimization.; Short model construction times allow more ideas to be explored in less time. This leads to shorter product time-to-market and more thorough design-space exploration. This also allows researchers to evaluate new design ideas faster, to efficiently evaluate ideas in the context of many designs, and, perhaps, develop a more fundamental understanding of microarchitecture due to these broader evaluations.
机译:为了确定最佳的处理器设计,设计师探索了广阔的设计空间。为了评估候选设计的质量,设计人员构建并使用模拟器。不幸的是,模拟器构建是此设计空间探索的瓶颈,因为现有的模拟器构建方法会导致较长的模拟器开发时间。这个瓶颈将探索限制在少数设计中,有可能降低最终设计的质量。本文介绍了一种快速构建高质量模拟器的方法。特别是,它检查结构建模是减少构造时间的一种方法,因为它消除了许多建模方法中管理设计复杂性所需的多余工作,包括使用顺序语言对模拟器进行编程。本文还描述了如何克服结构建模中常见的局限性,即通过基于组件的重用避免了跨模型的组件规范工作的摊销,从而增加了构建时间。首先,某些耗时的指定设计部分不能从重用中受益,重用是管理停顿信号(即,时序控制)的逻辑。其次,由于要实例化它们,必须理解很多细节,因此具有足够灵活性以享受重用的组件在实践中通常不会被重用。本文通过以下方法解决了这些问题:(1)提出了对时序控制的新见解,使时序控制可以在可重用组件之间进行分配。 (2)描述编程语言技术(例如多态和面向方面的编程)的应用,以允许创建易于重用的灵活组件。 (3)在存在上述特征的情况下,允许对模型进行静态分析;本文提出的技术体现在自由仿真环境(LSE)中。 LSE用户已经看到模型开发时间减少了一个数量级。他们的模型是高质量的。它们准确,具有足够的仿真速度,并且与用于可视化和优化的静态技术兼容。较短的模型构建时间使您可以在更短的时间内探索更多的想法。这样可以缩短产品的上市时间,并进行更彻底的设计空间探索。这也使研究人员可以更快地评估新的设计构想,在许多设计的背景下有效地评估构想,并可能由于这些更广泛的评估而对微体系结构有了更基本的了解。

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