A Mechanism Study of High-K Dielectric Quality and Metal Gate Al Diffusion Affecting PPU Transistor Threshold Voltage

摘要

High-k /metal replace SiO2/polysilicon as gate stack enables transistor size continuously scaling down. In this paper, the Vt (threshold voltage) instability mechanism of 28 nm PPU (p-type pull up) transistors in HKMG SRAMs (static random access memory) is investigated. A defect-assisted Al diffusion and dipole formation model is proposed to explain this phenomenon. Vt up-shift level of PPU transistor is dominated by the formation amount of dipoles, which are relied on both Al diffusion amount and defect density of high-k layer. Furthermore, reducing PNA (post nitridation anneal) temperature is demonstrated to be effective to suppress the Vt up-shift of PPU transistors. And this Vt adjustment is much more convenient than altering the metal gate stack to block Al diffusion.