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Numerical Study of the VDMOS with an Integrated High-K Gate Dielectric and High-K Dielectric Trench

机译:集成高k栅极电介质和高k电介质沟管VDMO的数值研究

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The VDMOS with an integrated high-k gate dielectric and high - k dielectric trench is investigated in this paper. The high-k (HK) dielectric is applied both for the gate dielectric and trench, which improves the performance without increasing the process complexity. First, HK dielectric trench makes the electric field distribution of the drift region more uniform, thus improving breakdown voltage (BV). Second, the HK dielectric trench assists the depletion of the drift region, thereby increasing the doping concentration of the drift region and decreasing the specific on-resistance (Ron, sp). Third, the HK gate dielectric decreases the threshold voltage (Vth) and increases the transconductance (gm) of the device. Simulation results show that the new VDMOS has a better breakdown, output, and conduction characteristics when compared to the sidewall HK dielectric VDMOS (SWHK VDMOS) and conventional VDMOS (Con VDMOS).
机译:本文研究了具有集成的高k栅极电介质和高k电介质沟槽的VDMOS。 高k(HK)电介质用于栅极电介质和沟槽,这改善了性能而不增加过程复杂性。 首先,HK介电沟槽使得漂移区域的电场分布更均匀,从而改善击穿电压(BV)。 其次,HK介电沟槽有助于漂移区域的耗尽,从而增加漂移区域的掺杂浓度并降低特定的导通电阻(RON,SP)。 第三,HK栅极电介质降低阈值电压(Vth)并增加器件的跨导(GM)。 仿真结果表明,与侧壁HK电介质VDMOS(SWHK VDMOS)和传统的VDMOS(CON VDMOS)相比,新VDMO具有更好的击穿,输出和传导特性。

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