A Design of 6-bit 125-MS/s SAR ADC in 0.13-#x00B5;m MM/RF CMOS Process

摘要

The design of a 6bit 125MS/s Successive Approximation (SAR) Analog to Digital Converter (ADC) that uses modified switching technique has been presented in this paper. This modified switching technique requires only half the number capacitors and achieves a switching energy reduction of about 91.5% when compared with conventional SAR ADC approach. This scheme also reduces by half the DAC capacitor array output settling time during bit cycling sequence. This SAR ADC with modified switching technique has been designed and simulated in UMC 0.13u MM/RF CMOS process. This design works with the clock frequency of 1GHz achieving a maximum sampling rate of 125MS/s and consumes 5.16mW power with 1.2V supply voltage and 800mVpp differential input range. The simulated dynamic performance indicates an SNDR and SFDR of 37.97dB and 54.35dB respectively.