A 2-bit higher radix analog-to-digital converter (ADC) circuit consisting of a combination of a pipelined ADC(and a set of cascaded current comparator cell has been proposed. The ADC generates multi-valued logic outputs rather than the conventional binary output system. The design is implemented using 0.13|im CMOS process. The performance analysis of the design shows desirable performance parameters in terms of response and low power consumption. The ADC design is suitable for the needs of mixed-signal integrated circuit design and can be implemented as a conversion circuit for systems based on multiple valued logic design.
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机译:提出了一种由流水线ADC(和一组级联电流比较器单元的组合)组成的2位高基数模数转换器(ADC)电路,该ADC产生多值逻辑输出,而不是传统的二进制输出系统,该设计采用0.13 | im CMOS工艺实现,对性能的分析表明在响应和低功耗方面具有理想的性能参数,ADC设计适合混合信号集成电路设计的需求,并且可以可以作为基于多值逻辑设计的系统的转换电路来实现。
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