Design of a 2-bit multi valued analog-to-digital converter

摘要

A 2-bit higher radix analog-to-digital converter (ADC) circuit consisting of a combination of a pipelined ADC(and a set of cascaded current comparator cell has been proposed. The ADC generates multi-valued logic outputs rather than the conventional binary output system. The design is implemented using 0.13|im CMOS process. The performance analysis of the design shows desirable performance parameters in terms of response and low power consumption. The ADC design is suitable for the needs of mixed-signal integrated circuit design and can be implemented as a conversion circuit for systems based on multiple valued logic design.