An ADC is synthesized entirely from Verilog code in 90nm digital CMOS using a standard digital cell library. An analog comparator is generated by cross-coupling two 3-input NAND gates. The random comparator offsets are used as the ADC references and are Gaussian. An implicitly aligned three-section piecewise-linear inverse Gaussian CDF function on chip linearizes the output. SNDR of 35.9dB is achieved at 210MSPS.
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