Silicon Trench Etch Uniformity Improvement for Microloading and Macro-to-Macro Loading for sub-14nmNode

摘要

Self-Aligned Double Patterning (SADP) has been used as a promising solution for advanced nodes (sub-14nm) because of fewer overlay problems and better process tolerance. However, SADP can generate process variations such as “pitch-walking” as a by-product of inline Critical Dimension (CD) and spacer errors. Pitch-walking can impact downstream operations, causing variation of etched depth or amount due to microloading. Because of the inherent SADP impact, it is critical to carefully manage and minimize microloading and macro-to-macro loading (isolated and dense pattern) impacts. In this paper, we report a test and demonstration of plasma etching conditions that can be applied in advanced nodes beyond 14nm patterning to relieve trench depth sensitivity to incoming CD variations caused by multipatterning and macro-to-macro loading impacts from pattern density. Our result showed that lower RF duty cycle, higher bias voltage, and higher etchant flow can reduce 50% of the depth variation to incoming CD variations caused by multipatterning in previous steps and 75% of the depth differences between dense and isolated pattern areas for macro-to-macro loading.