Non-Uniform Yield Optimization for Integrated Circuit Layout Considering Global Interactions

摘要

In a previous work we have shown a yield optimization metric and a technique that considers the effects of several types of yield enhancement methods for a given layout. Those findings suggested that it is important to consider two types of yield tradeoffs, local tradeoffs where addressing one yield loss mechanism degrades others in the immediate vicinity of the correction (local optimization window), and global tradeoffs where the net effect of the correction can be fully accounted only when considering neighboring optimization windows. Such conclusion was derived from the fact that the locally optimized layouts did not completely realize the theoretically optimal yield, which was obtained from the assumption that global tradeoffs could be fully resolved. This work focuses in the contribution that such global tradeoffs have on the final yield score when accounted properly during the optimization.While the previous work focused only in selecting the corrections that locally improved the yield score, this work evaluates the global interactions before and after a change, and the correction is only accepted if it improves the global score. While the global optimization requires a more expensive computational process, the intention of this work is to determine how close the optimal layout can be from its theoretical limit. Since the optimization is performed and evaluated under four different types of processes in which the failure mechanisms vary in relative importance, it is possible to derive conclusions as to the need of considering global effects when trading off runtime requirements with quality of the correction.