65nm mask CD qualification on critical features through simulation based Lithography Verification

摘要

For leading edge technologies, mask critical dimension (CD) errors consume a substantial part of the total wafer CD budget. Moreover, the strong optical proximity effects (OPE) can make the impact of a CD error on the mask significantly worse on wafer. At the same time, the mask making capabilities as far as CD control can barely keep up with the wafer fab requirements. To assess the overall mask quality ever more mask CD measurements are taken in the mask qualification process. These measurement points are increasingly placed in the main die area and are often selected in a more or less random fashion. An improved assessment of the mask CD quality can be achieved by taking advantage of the lithography verification step. The wafer simulation capability in the Silicon versus Layout (SiVL) tool is used to identify the high mask error enhancement factor (MEEF), error prone locations on a critical layer. The mask CD qualification process can be improved by including these poor MEEF and error prone sites. In this work, an automated flow is presented in which mask qualification sites are selected based on simulated wafer image contrast.