An Efficient Implementation of Secure Hash Algorithm SHA-512

摘要

A series of recent papers have demonstrated collision attacks on popularly used hash algorithms,including the widely deployed MD-5 and SHA-1 algorithm. To assess this threat, the natural response has been to evaluate the extent to which various protocols actually depend on collision resistance for their security, and potentially schedule an upgrade to a stronger hash algorithm. We proposed an efficient implementation of the newly proposed draft hash standard SHA-512. The proposed architecture exploits the benefits of parallel computer through precomputation of intermediate temporal values. Parallel computer is based on the decomposition of the SHA-512 expression to separate information dependencies and independencies. This allows pre-computation of intermediate temporal values in parallel to the calculation of other independent values. The proposed SHA-512 was prototyped and verified using a XILINX FPGA device. The implementation's characteristics are compared to the competitive implementations proposed by other researchers. On a VIRTEX (XCV1000E-8)FPGA device, the proposed SHA-512 is capable of a throughput of 957 Mbit/s, with only 2600 slices usage,respectively. In addition, it can be integrated in security systems which are used for the implementation networks for wireless protocols, with special needs of integrity in data transmission.