Phase Mismatch Detection and Compensation for PLL/DLL Based Multi-Phase Clock Generator

摘要

Device mismatch and systematic imbalances in the physical design can cause static phase mismatch in a PLL/DLL based multi-phase clock generator and degrade performance. This problem gets worse in deep sub-micron technologies. Interleaved transceiver architectures require precise clocking to maximize data rate and minimize bit errors. In this paper, a static phase mismatch compensation scheme for multiple sampling clocks is proposed and tested in an adaptive-bandwidth mixing PLL/DLL based multi-phase clock generator. The proposed charge pump compensator and power efficient phase-averaging network together reduce the static phase mismatch standard deviation by 37% when operating in DLL mode. A simple and robust duty-cycle correction circuit exhibits a small residual error of 0.65% across a wide range (36% to 49%) of input clock duty-cycle values