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- High Resolution Multi-Phase Clock Generator Based On Array Of Delay Locked Loops

机译:-基于延迟锁定环阵列的高分辨率多相时钟发生器

摘要

PURPOSE: A high resolution multi-phase clock generation circuit by using an array delay locked loop is provided to make multi phase clocks without limiting the number of delay cells of the main delay locked loop and the number of delay cells of the auxiliary delay locked loop. CONSTITUTION: A high resolution multi-phase clock generation circuit by using an array delay locked loop includes a main delay locked loop and a plurality of auxiliary delay locked loops. Each of the main delay locked loop and the auxiliary delay locked loops is provided with a delay line having a plurality of delay cells to generate a multi phase clock, a phase comparator to compare the signal passing through the delay line with the comparison signal, a charge pump circuit to generate the signal being proportion to the phase difference between two signals and a filter the filtered output signal of the charge pump as a control voltage of the delay cells in the delay line. The high resolution multi-phase clock generation circuit is characterized in that each of the main delay locked loop and the auxiliary delay locked loops utilizes a different phase clock signal from each other.
机译:目的:提供一种通过使用阵列延迟锁定环的高分辨率多相时钟生成电路来制作多相时钟,而不会限制主延迟锁定环的延迟单元数和辅助延迟锁定环的延迟单元数。构成:一种利用阵列延迟锁定环的高分辨率多相时钟生成电路,包括一个主延迟锁定环和多个辅助延迟锁定环。主延迟锁定环和辅助延迟锁定环中的每一个都设置有具有多个延迟单元的延迟线,以生成多相时钟;相位比较器,将通过延迟线的信号与比较信号进行比较;电荷泵电路产生与两个信号之间的相位差成比例的信号,并对电荷泵的滤波后输出信号进行滤波,作为延迟线上延迟单元的控制电压。高分辨率多相时钟发生电路的特征在于,主延迟锁定环和辅助延迟锁定环中的每一个利用彼此不同的相位时钟信号。

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