- High Resolution Multi-Phase Clock Generator Based On Array Of Delay Locked Loops

摘要

PURPOSE: A high resolution multi-phase clock generation circuit by using an array delay locked loop is provided to make multi phase clocks without limiting the number of delay cells of the main delay locked loop and the number of delay cells of the auxiliary delay locked loop. CONSTITUTION: A high resolution multi-phase clock generation circuit by using an array delay locked loop includes a main delay locked loop and a plurality of auxiliary delay locked loops. Each of the main delay locked loop and the auxiliary delay locked loops is provided with a delay line having a plurality of delay cells to generate a multi phase clock, a phase comparator to compare the signal passing through the delay line with the comparison signal, a charge pump circuit to generate the signal being proportion to the phase difference between two signals and a filter the filtered output signal of the charge pump as a control voltage of the delay cells in the delay line. The high resolution multi-phase clock generation circuit is characterized in that each of the main delay locked loop and the auxiliary delay locked loops utilizes a different phase clock signal from each other.