Chip assembly

摘要

Design teams designing modern multi-million gate systems-on-chip (SoCs) are being adversely affected by the lack of desired chip assembly solutions in addition to the challenges due to variability in nanometer technologies. Abstractions, bad pin assignments, incorrect block budgets, incorrect clock insertion delay budgets, lack of variability aware analysis engines, and lack of concurrent optimization capabilities often lead to chip failures, reduced yield, missed schedule and lost performance.Due to the late surprises in chip assembly, design teams have rushed to incorporate chip assembly as part of concurrent engineering with the block implementation. A new paradigm and tool set that enables efficient multi-million gate chip assembly while concurrently analyzing and optimizing across all variability scenarios is critical for nanometer hierarchical flows.In this paper we will review chip assembly challenges and discuss the requirements of an implementation system that comprehensively addresses all the issues.