High Speed Low Power CMOS Comparator Dedicated to 10it, 20MHz Pipeline ADCs for RF Applications

摘要

In this paper, a differential comparator featuring a high speed of conversion, is described and analyzed. The designed comparator is intended to be implemented in a 10bit, 20MHz pipeline Analog-to-Digital Converter dedicated to RF WLAN applications. This comparator is based on the switched capacitor network using a two-phase nonoverlapping clock. The analyses and simulation results which have been obtained using 0.8μm CMOS AMS process parameters, with a power supply voltage of 5V and an input common mode of 2-3V, show that this comparator exhibits a propagation delay of 1 7.3ns, a good accuracy and a low power consumption of about 0.8mW. The predicted performance is verified by analysis and simulations using PSPICE tool.