Full Parasitic Capacitance Model of Diode-Class ESD Protection Structures for Mix-Signal and RF ICs

摘要

A full parasitic capacitance model of diode-class ESD structures is presented in this paper, including not only the reversed-bias capacitance model in the circuit normal operation but the forward-bias capacitance model under the ESD stress. This model successfully calculates the ESD-induced capacitances which degrade the high-speed mix-signal and RF IC performances, and also deals with the puzzle why diode-class structures have a low discharge level with a small turn-on resistance. And a novel parameter CESDV, which is named as the parasitic capacitance unit kV ESD level for the ESD device, is also proposed. The experimental results imply that the MOS-bounded diode has a CESDV about 15fF/kV, far smaller than the normal diode about 30fF/kV. It is shown that the MOS-bounded diode is an appropriate choice for the high-speed mix-signal and RF ICs ESD protection.