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Effect of die attach configuration in stacked die packages

机译:堆叠管芯封装中管芯附着配置的影响

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摘要

To accommodate the ever-increasing pressure of reduction in size, weight and cost, while provide more functionality and better reliability, many innovative electronic packaging solutions have been developed. Among them, stacked die packages offer smallest foot-print and thinnest profile in a cost-effective way and have been widely implemented in ASIC, memory, Ethernet controller, and other packages. However, new challenges keep emerging as more dies are stacked up and die thickness decreases to 50 to 75 /spl mu/m level. In this paper, the improvement in die attaches to better suit stacked die configuration was discussed, including replacement of dummy die (spacer die) with spacer die attach pastes, adjustment of die attach properties and geometry to minimize molding compound/die attach delamination at die overhang area, comparison of film and paste die attaches. The detailed comparison in warpage and stresses was supported by finite element analysis.
机译:为了适应减小尺寸,重量和成本的不断增长的压力,同时提供更多的功能和更好的可靠性,已经开发了许多创新的电子封装解决方案。其中,堆叠式裸片封装以经济高效的方式提供了最小的占地面积和最薄的外形,并已广泛应用于ASIC,存储器,以太网控制器和其他封装中。然而,随着更多模具的堆叠和管芯厚度减小到50至75 / spl mu / m的水平,新的挑战不断出现。在本文中,讨论了对芯片贴装的改进,以更好地适应堆叠的芯片配置,包括用间隔贴片芯片贴装膏替换虚拟芯片(垫片芯片),调整芯片贴装特性和几何形状以最大程度地减少模塑料/芯片贴装在芯片上的分层悬垂区域,比较薄膜和粘贴模头的附着力。翘曲和应力的详细比较得到了有限元分析的支持。

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