Applications of Newly Developed Positive Photosensitive Block Co-Polyimides to Microelectronic Packaging Processes

摘要

Meeting the challenging market-defined needs of CSPs (chip sized packages) industry requires a new substrate technology that provides higher I/O densities, higher performance, thinner and lighter packaging structures than previously available solutions. In this paper, the first applications to CSP interposer (CSP-IP) processes by newly developed positive photosensitive block co-polyimides (PPI), which P I R&D Co., Ltd. of Japan has commercialized recently, are discussed. Block co-polyimides are prepared in organic polar solvents by the sequential addition co-polymerization process in the presence of the binary catalyst, which has been described in US patents by the author. PPI polymer solutions are derived from block co-polyimides including photo-sensitizers. Advantages of newly developed PPIs from block co-polyimides are as follows; 1) no imidization process needs at high temperature, 2) PPIs have strong adhesive ability to Cu, Al and Si wafers, 3) thinner thickness polyimide films are available with high durability, 4) positive photo-pattern are available with high resolution, 5) PPIs are high temperature Tg materials. In CSP-IP packaging processes by PPI, it is shown that PPI's UV-lights resolution workability brings highly uniformed 20 microns diameter via hole, and also, highly uniformed solder bumps attached on the polyimides layers. PPI requires no imidization process after drying and curing in the processes, accordingly, the whole heat requirements in the CSP-IP processes are below 200°C, which enables to CSP-IP the additional layers of lead I/O patterning between solder bumps interstice without any solder bump deformations, that provides higher I/O densities, size reductions to the new CSP-IP. PPI's pin-holeless performance using black masks in the processes brings CSP-IP production cost keeps very low-level, and it is possible to coat PPI polymer solution directly on silicon wafer easily and to produce the wafer CSP with high production yield, which keep this wafer CSP processes quite a competitive low cost. Thinner layered CSP-IP packages by PPI described above could be applied to the 3D-stacked CSP package features.