Three-dimensional (3D) LSI has a big impact on packing density for high-performance LSI systems. This paper presents a new chip-on-chip technology using Cu chip through plugs for reducing interconnection resistance and results of the first demonstration for stacking actual LSIs, 0.4 μ m-design rule 64Mbit NAND flash memories to produce 128Mbit NAND flash memory. The 3D flash memory consists of Cu through plugs (40 μ m in diameter-60 μ m depth) in Si substrate and bumps for stacked chips. The chip-on-chip process flow is summarized as follow. First, 64Mbit NAND flash memories were fabricated by standard wafer process. Next, the deep holes for chip through plugs were formed by a developed high-speed RIE. The etching rate of Si-substrate was more than 50 μ m/min. The holes were filled using Cu electroplating. Then, the wafer was thinned from the backside by grinding and dry etching until the chip was exposed through plugs. After dicing, the good chips selected by electrical test were stacked with Cu plug and solder bumps. The electrical characteristics of stacked chips were evaluated for application as a flash memory. It was found the both memories functioned normally at serial read cycle of 50ns. The stacked LSIs have been fabricated using a new chip-on-chip technology. It was concluded that the new chip-on-chip technology is one of the most promising solutions for future high-density and high-performance LSI system.
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