Plasma charge-induced corrosion of tungsten-plug vias in CMOS devices

摘要

Plasma charge-induced corrosion of tungsten plug vias, where part of the via surface is exposed to the chemical solution after metal-2 etch by photolithographic misalignment with upper metal lines, was investigated. Some electrochemical tests and plasma damage monitoring were done to study the corrosion mechanism. The configuration of circuits was also investigated to understand the pattern dependency of the plasma damage and the corrosion. It is believed that the positive charges on the metal lines and P/sup +/ active region of the PMOS, developed during dry etching and ashing, are enhancing the corrosion of tungsten during stripping. The plasma-less O/sub 3/ asher applied to the ashing process reduced the plasma damage and did not produce empty vias on the wafer.