Analysis and control of hysteresis in PD/SOI CMOS

摘要

A new methodology to characterize and analyze hysteresis in PD/SOI CMOS inverter-based circuits, including its true worst case, is defined, and new insight into the underlying physics is provided. The methodology is used to explore novel device/circuit designs for controlling hysteresis as the PD/SOI CMOS technology is scaled to >100 nm.