Equivalent circuit modeling of interconnects from time domain measurements

摘要

A technique for the equivalent circuit modeling of interconnects having discontinuities such as bends, steps, and junctions in high-speed circuits and packages is developed. The circuit models are extracted from time domain reflection (TDR) measurements. The simulated results for the circuit models are compared with the measured data to validate the accuracy of the circuit model. The proposed method can be used to help validate circuit models based on field-theoretic techniques as well as used as an independent tool to synthesize circuit models for general nonuniform or interacting two- and three-dimensional interconnects.