A Novel Warpage Reinforcement Architecture with RDL Interposer for Heterogeneous Integrated Packages

摘要

Over the past two decades, the multi-functions of portable electronic devices have a significant influence to change the daily life of people. To meet the requirements of short transmission path of signals, and high I/O counts, ultrathin packaging technology and novel packaging architectures are continuously progressed in accordance with the emergence of advanced technologies in global semiconductor industry. Currently, the architecture of fan out panel-level packaging (FOPLP) grows into the mainstream to meet the essentials of three-dimensional chip stacking and heterogeneous integration. Some researches suggested that the fine metal trace small than 5μm/5μm (line-width/spacing) has been carried out by using redistributed layer (RDL) first interposer technology. In the meanwhile, the package on package framework was introduced for connecting application processor and stacked memory chips, which have been gradually implemented the above-mentioned portable electronic devices. However, the warpage issue of the top and bottom packages are always a critical issue while assembled. In order to solve this issue, an additional reinforcement frame, integrated with RDL interposer is proposed to reduce its deformation caused by coefficient of thermal expansion (CTE) mismatch among the materials of packaging components. The design of reinforcement frame is 15 mm x 15 mm with a 12 mm x 12 mm cavity. There are 540 interconnections with a 300 gm of pitch at the periphery of the present package. To estimate the reliability of abovementioned novel package with efficiency, a non-linear process-oriented finite element analysis (FEA) is approached. In addition, the technique of equivalent material characteristics is also needed into FEA model to simplify the complexity of packaging structure. Finally, the better combinations to control the warpage of the present novel packaging structure through choosing the type of MUF. The warpage of packaging is obtained via the simulation methodology and provided as the designed guideline of related packaging architectures.