Three Dimensional Integration and On-Wafer Packaging for Heterogeneous Wafer-Scale Circuit Architectures; Conference paper with briefing charts

摘要

Advanced Network Centric Warfare (NCW) systems require a new generation of circuits with deployable, agile, versatile, lethal, survivable and sustainable capabilities. The super-heterodyne radio architecture in present systems necessitates multiple passive off-chip components including IF filters adapted to the channel filtering requirements to support different standards. A newer direct conversion (including low IF) architecture has evolved that lends itself to a single- or few-chip mixed signal implementation although performance is compromised primarily because of the loss and finite Q of on-chip passives leading to low RF efficiency, increased power consumption and high phase noise. The potential of using high density, low-loss interconnects and integrated high quality passives has been shown to provide maximum benefit for integrated microwave systems. Both design cycle times and system performance have been advanced through the use of high-resistivity silicon in a unique Si-based Self-Aligned Wafer Level Integration Technology (SAWLIT), that was developed as part of this project. In this technology the CMOS or SiGe ICs are integrated within the Si interposer using low-loss interconnects with a definition better than 1 micron. This integration approach allows the removal of passives from the expensive IC chip and their integration on the interposer for lower cost and better performance. Additionally, the use of a multi-layer package integrated with the interposer allows for the high density integration of high quality components such as cavity based filter with unloaded Q's > 1500s. In this paper we will present the implementation of the interposer concept on a transceiver architecture that easily lends itself to a threedimensional heterogeneous integration along with the passives that make this integration possible. The three-dimensional circuit architecture will be demonstrated on a 10GHz CMOS receiver.