Monolithic three-dimensional (3D) wafer-scale integration offers increased performance of digital ICs, heterogeneous integration of alternative technologies and lower manufacturing cost for electronic and optoelectronic systems. After a brief discussion of alternatives to alleviate interconnect limitations of Cu/low-k with minimum feature size < 50 nm, we focus on 3D wafer-scale integration processing issues and technology feasibility. The packaging of 3D ICs is highlighted and compared to conventional 2D ICs and stacked chip-scale packaging. Finally, a grand challenge is considered, a complete system in a PCMCIA-sized package.
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