Vertically stacked RF switches by wafer-scale three-dimensional integration

摘要

Vertically stacked RF switches implemented by wafer-scale three-dimensional (3D) integration of three completely fabricated silicon-on-insulator wafers are demonstrated. The individual switch performance was maintained through the 3D integration process while the signal path is shortened by vertical interconnects. The footprint of the switch can be shrunk in proportion to the number of tiers it is distributed between, demonstrating the potential of significant size reduction of multiple-throw switches commonly required in many applications.