The demand for high performance computing is on the rise with the dominance of applications that process big data. Most of these applications are dominated by arithmetic operations, primarily multiplication and addition. Many of these algorithms, e.g., in the machine learning domain, can tolerate some amount of arithmetic error, especially in the low-order bits. Hardware designers can leverage this observation to simplify the hardware design. Although prior work has demonstrated the benefits of approximate arithmetic in the context of one-off hardware designs, what is presently lacking is a systematic methodology to generate highly-optimized arithmetic components that meet a user-specified level of error tolerance. This paper introduces one such tool, which generates single-cycle approximate adders along with speculative adders which perform multi-cycle error correction. The underlying intellectual contribution is a family of approximate 1-bit Full Adders (XFAs), which vary in terms of accuracy, delay, area, and power consumption. Our tool, CAL, constructs larger adders using XFAs as building blocks, effectively allowing the user to sacrifice accuracy in order to improve the three aforementioned metrics. The experimental analysis demonstrates improvements in both accuracy and efficiency compared to state-of-the-art approximate adder designs published by others, and validates the capabilities of our speculative implementations.
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