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Study of wafer warpage for Fan-Out wafer level packaging: finite element modelling and experimental validation

机译:扇出晶圆级封装的晶圆翘曲研究:有限元建模和实验验证

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Wafer warpage is a big challenge during wafer process in Fan-Out Wafer-Level-Packaging (FOWLP). It is crucial to keep warpage low as much as possible for successful process integration. The warpage is mainly due to the Coefficient of Thermal Expansion (CTE) mismatch between the involved materials during temperature changes. Furthermore, warpage of molded wafers depends on material properties. Therefore, accurate material characterization has great importance. In this paper, thermal-mechanical properties of the used polymeric materials were measured using nanoindentation and Stereo-Digital Image Correlation (SDIC). In this study, warpage of molded wafers with and without Temporary Bonding Adhesive (TBA) is investigated during heating to 200°C and cooling down to room temperature. SDIC technique was used to measure the warpage of molded wafers. Finally, Finite Element (FE) simulations were carried out using as input the measured thermal-mechanical properties. A comparison between warpage measurements and FE simulation at different temperatures showed a good agreement.
机译:在扇出晶圆级封装(FOWLP)中,晶圆翘曲是晶圆加工过程中的一大挑战。对于成功的过程集成而言,保持尽可能低的翘曲至关重要。翘曲主要是由于温度变化期间所涉及材料之间的热膨胀系数(CTE)不匹配。此外,模制晶片的翘曲取决于材料特性。因此,准确的材料表征非常重要。在本文中,使用纳米压痕和立体数字图像相关性(SDIC)测量了所用聚合物材料的热机械性能。在这项研究中,研究了在加热到200°C并冷却到室温期间,有无临时粘合胶(TBA)的模制晶片的翘曲。 SDIC技术用于测量模压晶片的翘曲。最后,使用测得的热机械性能作为输入进行了有限元(FE)模拟。在不同温度下的翘曲测量和有限元模拟之间的比较显示出很好的一致性。

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