Modeling Performance and Thermal Induced Reliability Issues of a 3nm FinFET Logic Chip Operation in a Fan-Out and a Flip-Chip Packages

摘要

We investigate self heating and cooling of a logic chip in two different package types during operation of a FinFET logic chip built with 3nm design rules. It is critical to consider thermal transport in the narrow fin and in the narrow interconnect wires, where heat transport slows down by over 10x due to acoustic phonon scattering at the interfaces between narrow layers, so we perform detailed 3D analysis of a single FinFET transistor and a FinFET inverter from a clock tree network. For the thermal behavior of a package, we employ an efficient modeling methodology that uses a set of thermal RC networks to represent the package thermal environments. The package thermal resistance extraction accounts for the heat conduction path dependence. The thermal capacitances are needed to characterize the dynamic and transient behaviors of the devices. Whereas the power excitation is applied at the device position inside the package, the thermal impedance at the response thermal contact is then computed during the solution of the transient heat equation. Then, TCAD (Technology CAD) simulation is performed to analyze a hot spot inside FinFET. For the flip-chip and fan-out packages, various material and geometry options are explored for constituent components to guide packaging design and material engineering.