A CMOS Perimeter Gated SPAD Based mini-Digital Silicon Photomultiplier

摘要

In this paper, a CMOS perimeter gated single photon avalanche diode (PGSPAD) based mini-digital silicon multiplier (SiPM) is presented. A PGSPAD's additional terminal tunes the dark count, efficiency, and measurement range of the device. Spatial and temporal data compression schemes, reduce the total readout electronics and improve fill factor (FF). For a more compact, low power implementation, a single analog counter provides temporal integration of PGSPAD avalanche events. An event generator realizes the fully digital asynchronous address event representation readout at the top level of the detector. The SiPM is implemented in standard 0.5 μm CMOS process and simulation results show temporal compression and dead time improvement by 10 and 25%. The designed PGSPAD mini-digital SiPM is suitable as the pixel of PGSPAD digital SiPM for nuclear imaging applications.