Chip Stackable, Ultra-thin, High-Flexibility 3D FOWLP (3D SWIFT® Technology) for Hetero-Integrated Advanced 3D WL-SiP

摘要

Fan-out wafer level packaging (FOWLP) is one of the latest technologies to meet the requirements of high performance and thin form-factor, especially for mobile application processors. To achieve a simple path way and thinner package form, many outsourced semiconductor assembly and test (OSAT) suppliers and foundries provide FOWLP capabilities. Most solutions are limited to the bottom 2D package area with a package on package (PoP) stacking structure to communicate logic to memory or a peripheral chip beyond the 2D distribution area. This means that communication between heterogeneous chips has more power and signal loss by PoP interconnection to reach hetero-chip functions through bulk solder ball joints and printed circuit board (PCB) laminated routing with more coarse trace pattern than a fan-out (FO) redistribution layer (RDL pattern). To improve this situation, high performance heterogeneous integration has been simulated and successfully realized with the novel 3D Silicon Wafer Integrated Fan-out Technology (SWIFT®) prototype as chip stackable, ultra-thin, high flexibility FOWLP for the first ultimate 3D packaging. Also, this has been proven to be a highly flexible and cost-effective structure with a low-risk process flow, low package warpage, stable electrical performance, and good reliability performance. The form-factor of the 3D SWIFT design with various structure options is as much as 45% thinner than PoP technology.