Study on the structure of vertical Through Silicon Via with aspect ratio 2.5:1 for CMOS image sensor

摘要

Through Silicon Via(TSV) plays a important role as the interconnect in three dimensional miniaturization of electronic device. In this paper, the process flow of vertical TSV with aspect ratio 2.5:1 is presented for CMOS image sensor. The process includes wafer bonding, thinning, TSV etching, electroplating, wet etching, passivation, Ball Grid Array(BGA) and dicing. The measured low resistance of interconnection shows high current carrying capability of the TSVs. The simplified process provides a cost-effective solution for 3D integration.