Design and Analysis of Gate Engineered Gate-AII-Around (GAA) Charge Plasma Nanowire Field Effect Transistor

摘要

The reported work shows the effect of gate engineering techniques upon Gate All Around (GAA)- Charge Plasma (CP)- Nanowire FET. The proposed architecture includes both dual material gate (DMG) and Gate stacking (GS) techniques making it a GAA - Dual Material Gate (DMG) - Gate Stack (GS) - CP-NWFET device for better electrostatic control over the channel. As it is a charge plasma device, a proper common work function is used for n^{+source/drain electrode to minimize the threshold voltage fluctuations. Gate stacking (SiO2 + High-k) helps in increment of transfer characteristics of the device. A comparison is made in between GAA-CP-NWFET, GAA-GS-CP-NWFET, GAA-DMG-CP-NWFET and GAA-DMG-GS-CP-NWFET devices. The analog parameters are analysed for all the four devices and a comparison is made with GAA-DMG-GS-CP-NWFET device. With the proven advantage of gate all around structures, a better controllability over gate is already exists. Addition of these gate techniques, an improved performance is recorded for the proposed GAA device. The GAA-DMG-GS-CP-NWFET device has shown low OFF-state current and high ON-state current proving its ability with incorporating gate engineering techniques for the future nanoscale regimes.}