Development of Novel High Density System Integration Solutions in FOWLP-Complex and Thin Wafer-Level SiP and Wafer-Level 3D Packages

摘要

Expanding FOWLP (Fan-Out Wafer-Level Packaging) from mainly 2D single or multi die solutions to 3D stacked multi-die solutions with SMDs integration, is of crucial importance to meet the requirements arising from new markets such as IoT/IoE and Wearables. This drives the development of new capabilities and technology breakthroughs in the current FOWLP process. One of the most hailed capabilities of FOWLP is the heterogeneous high-density system integration in a package. Wafer Level System-in-Package (WLSiP) already integrates active dies, passive components and even already-packaged components, in a wide range of geometries and materials. Vertical interconnections enable FO-based WL3D solutions, thru Package-on-Package (PoP) assembly. The nature of FOWLP, being a substrate-less technology and using thin-film re-distribution layers, makes the package itself an active interposer. This concept allows very thin packages and PoP solutions, with excellent electrical and thermal behaviour compared to other packaging technologies. To accomplish the vertical package interconnect, or Thru Package Vias (TPV), required for package front to backside connections and 3D assembly, pre-formed vias solution was developed as the concept of choice at NANIUM for lower IO density and package body thickness from 200 to 400um. To allow the process on very thin Fan-Out wafers and, on the last stage, the double side RDL process to complete PoP solution, dedicated Temporary Wafer Bonding (TWB) and Debonding solution for FOWLP were developed and tested. This paper presents the approaches used to effectively enable FOWLP-based WLSIP and WL3D products: Pre-formed via solutions in three build-up options, from process development to reliability result, Wafer front-to-back RDL alignment solutions for high-accuracy 3D package, FOWLP TWB solution for WL3D/ PoP products, and stack-up/ stack-down solution for the final PoP implementation, when there is no space for additional die inside the WLSiP or due to the need to simplify routing complexity and reduce number of RDL's. Several demonstrators are built to demonstrate the above mentioned features, from a very thin, <;300μm body, 12×12mm2 WLSiP with double side RDL for stack-up PoP, to a WL3D solution for a stack-down PoP.