Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors

摘要

A high-yield nine carbon nanotube MOSFET (9-CN-MOSFET) SRAM cell that can tolerate the removal of metallic carbon nanotubes (m-CNs) is proposed in this paper. A functional yield model of carbon nanotube transistors and memory circuits is developed considering the spatial correlations of CNs in the channel arrays. The yield of the m-CN-removal-tolerant 9-CN-MOSFET SRAM array is increased by 21309x as compared to the previously published memory circuit that does not consider process imperfections. The read delay and worst-case write delay of the proposed 9-CN-MOSFET SRAM circuit are reduced by 29.05% and 22.30%, respectively, as compared to the previously published memory circuit in a 16nm CN-MOSFET technology.